1. Field of the Invention
The present invention generally relates to pipelined data processing systems. More particularly, the invention concerns systems for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition.
2. Description of Related Art
Competitive manufacturers in the computer industry are constantly finding new ways to boost the processing speed of their machines. One popular technique to increase processing speed is "pipelining", where certain hardware components or a software compiler assembles machine instructions into especially efficient sequences capable of executing with a modicum of time.
Pipelining is further enhanced with the use of the Very Long Instruction Word ("VLIW"), currently being researched by companies such as IBM Corporation. VLIW fine-grained parallelism exists at the machine instruction level within each task. A VLIW machine uses a compiler to search through a program for machine instructions capable of being executed simultaneously. These instructions are then assembled into a compound VLIW instruction. Each part of a VLIW instruction may control a separate part of hardware, such as an ALU, a path to main storage, or a path to a register. In one VLIW machine cycle these separate resources can all be used; as a result, several basic machine instructions can execute concurrently. Thus, each task can be completed in fewer machine cycles than is possible on a traditional uniprocessor. The so-called "turnaround time" from task initiation to task completion is therefore reduced, making the results available sooner.
As mentioned above, VLIW machines use compilers to construct compound machine instructions for execution by hardware. A well written compiler generates an instruction stream that keeps most of the available hardware resources busy doing useful work on most machine cycles. Accordingly, there are few machine cycles in which hardware resources are dormant.
Usually, this efficiency translates directly into an overall increase in processing speed. Under some conditions, however, problems can result from the heavy utilization of temporary hardware storage areas such as instruction registers, register files, general purpose registers, and the like. In particular, the rapid "back-to-back" execution of instructions can frustrate recovery from "exceptions" such as hardware/software errors, machine checks, and software exceptions. Due to the rapidity at which registers are updated, old data may no longer be available to restore registers to their respective states before occurrence of the exception.
A number of solutions to the foregoing problems have been developed, as described below.